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Resources and projects for FPGA design.
Page Last Updated 09/03/2012 10:39 PM
Contents:
1. VHDL - References and Tutorials:2. FPGA Manufacturers & Board Vendors:3. FPGA Prototyping Boards I Use:3.1 BurchED B3-Spartan2+ Board4. FPGA Design Tools:3.1.1 ICST525-01 PLL Clock divider3.2 BurchED B5-X300-Spartan2e Board
3.1.2 Notes on modifying the B3-SRAM module
3.1.3 Notes on adding a CF card
3.3 Digilent Spartan 3 Starter Board
3.4 Digilent Spartan 3E Starter Board
3.5 XESS XSA-3S1000, XST-3.0 & XSUSB3.5.1 IDE Compact Flash Interface.3.6 Memec Design / Avnet V4FX12LC
3.7 Altera / Terasic DE2-70 Cyclone 2
3.8 Altera / Terasic DE1 Cyclone 2
3.9 XESS XuLA Spartan 3A
4.1 Xilinx Web Pack ISE:5. FPGA Projects
4.2 Altera Quartus:
5.1 System16 - My Initial VHDL CPU Project6. VHDL & Verilog IP Resource Links:
5.2 Memio.zip Memory I/O Tool
5.3 Micro8 - A very simple microprocessor
5.4 Micro8a - Adding a Stack
5.5 Micro16 - Very Basic 16 bit machine
5.6 Micro16 - Processing Array
5.7 Motorola 8 bit CPUs
5.8 System01 - 6801 - Working (Incomplete I/O)
5.9 System68 - 6800 - Working
5.10 System05 - 6805 - Work in Progress
5.11 System11 - 68HC11 - Partly Working
5.12 System09 - 6809 SOC - Runs Flex9 with VDU and PS/2 Keyboard
5.13 System6801 - Wishbone Compliant 6801 for Altera by Michael Hasenfratz
1. VHDL - References and Tutorials:
The two most common languages used for FPGA design are VHDL and Verilog. I have chosen to use VHDL for my designs for no other reason than the reference books appeared to be a bit cheaper and more readily available. VHDL stands for Very high speed integrated circuit Hardware Description LanguageHere are some of the VHDL online Tutorials thrown up by Google:
VHDL-online - by Prof. Dr.-Ing. Wolfram H. Glauert, Universität Erlangen-Nürnberg
VHDL Introductory Tutorial - Green Mountain Computing Systems Inc.
Tutorial: Learn by Example - by Weijun Zhang, University of California Riversdale
VHDL Tutorial - Jan Van der Spiegel, University of Pennsylvania
VHDL Cookbook (pdf) - by Peter J. Ashenden - Dept. Computer Science, University of Adelaide South Australia (Hosted by Hamburg University).
VHDL Verification Course - www.stefanvhdl.com
VHDL Handbook - HARDI Electronics (Hosted www.cs.umbc.edu)
My good friend Anthony Burch up in Sydney has developed a series of FPGA training videos especially designed for newcomers to FPGA design. They are suitable for hobbyists, university students, commercial organizations and engineers wishing to learn about FPGAs. Membership to the web site is only AU$19.95 and gives you access to 18 videos.Tony offers the first 6 videos free as an introduction to give you an idea of what to expect.
The topics include:
- What to look for in selecting an FPGA board
- Downloading and installing the Xilinx Web pack software,
- Designing a simple logic circuit for the Xilinx Spartan 3E starter board,
- Using schematic capture, and
- Downloading the code to the FPGA board.
Tony has had many years of experience in developing FPGA systems, having designed the B3-Spartan2+ and B5-X300 FPGA boards, and add on modules.
Tony's videos were featured in Max Maxfield's Programmable Logic Design Line newsletter on the 21st August 2008.
http://www.diycalculator.com/ - Clive (Max) Maxfield's and Alvin Brown's DIY Calculator web site
This is Max & Alvin's web site for their book 'How Computers Do Maths' which describes a basic 8 bit microprocessor and the assembler routines for performing maths functions. Max & Alvin provide an emulator for their virtual 8 bit microprocessor CPU which can be downloaded from the web site. They have also produced a data book for their CPU chip along the lines of the assembly instructions manuals for the early 8 bit chips. The data data book is also available for download. The book provides an excellent introduction to basic micro-computing.
Heaps of books can also be found on Amazon, by using the key words 'FPGA', 'VHDL', Verilog', 'Xilinx' and 'Altera'.
Amr Ali has a number of slides entitled VHDL 360 by his friends Mohamed Samy and Samer El-Saadany
Synthesis ExamplesSynthesis Using ISE
Data Types and Operators
Data Types and Oporations Continued
Create Your First Model for a Simple Logic Circuit
Write More Complex ModelsWrite More Complex Models Continued
Modeling Finite State Machines(FSMs)
Structural Description
Post Place and Route Simulation
Simulation using ISIM
uCOS & VHDL Training
Amr, Samy and Samer also offer uCOS II & III on-line training, for embedded CPUs and online courses in VHDL for Xilinx FPGAs. They also give instructor lead courses for those who are interested. Courses are tools independent and are mainly based on simulations. Contact amraldo@hotmail.com for course details.
Electronic Forum for the Electrical Engineering Community. Covers Analog Design, RF Design, Power Management, Embedded Design, Test & Measure, Components & PCB Design. EEWeb have kindly offered to feature this web site on their home page on the 5th September 2011.
2. FPGA Manufactures & Board Vendors:
Here is a list of vendors of low price Xilinx (mostly Spartan) FPGA boards suitable for hobby use.Altera - FPGA Manufacturer (Cyclone, Arria, Statix)
Lattice - FPGA Manufacturer (XP, Mach, SC, EC, ECP)
Xilinx - FPGA Manufacturer (Spartan & Virtex)
Avnet (US)A wide range of Spartan 3, Virtex 2, Virtex 2 Pro, Virtex 4 and Virtex 5 boards
Too many to list. More intended for professional use.
Braemac (Australia)
Australian Altera/Terasic Distributor
BurchED (Australia)
Xilinx FPGA Video Guides
(Formerly Spartan2 B3 (XC2S200), B5 & B5-X300 (XC2S300))
Digilent Inc (US)
XUP (Virtex 2)
NetFPGA (Virtex2 Pro)
GENESYS (Virtex5)
OPUS (Virtex 5)
BASYS2 (Spartan 3E XC3S100E, XC3S250E)
NEXSYS2 (Spartan 3E XC3S500E, XC3S1200E)
Spartan3 Starter Board (XC3S200, XC3S1000)
Spartan3E Starter Board (XC3S500E, XC3S1600E)
Falulous Silicon
Alien Cortex Board Multicore softprocessor development platform by Bryan Pape.
Butterfly One (XC3S250E is $49.99 and the XC3S500E $74.99)
Seed Studio (Gadget Factory supplier)
Papilio One (XC3S250E board is $49.90 and the XC3S500E $64.90) and there are other suppliers in US and UK.
KNJN LLC (US)
RS232: Pluto (ACEX-1K), Pluto-II (Cyclone EP1K10), Pluto-3 (Cyclone II EP2C5)
Parallel: Pluto-P (ACEX EP1K10)
USB2: Saxo (Cyclone EP1C3), Saxo-L (Cyclone EP1C3 - Optional ARM CPU), Saxo-Q (Cyclone EP2C5 - 4 input ADC)
USB2: Xylo (Cyclone EP1C3), Xylo-EM (Cyclone EP2C5), Xylo-L (Spartan3E XC3S500E - NXP ARM CPU)
PCI: Dragon (Spartan2 XC2S100 PCI)
PCI-E: Dragon-E (Virtex5 XC5VLX20T PCI-E)
Trenz Electronics (Germany)
TE0140 Series (Spartan 3) Standard FPGA MicromodulesTE0300 Series (Spartan 3E) Industrial FPGA Micromodules
TE0320 Series (Spartan-3A DSP) Industrial Micromodule Series
Xess (US)
XSA-3S1000 - (Spartan 3 XC3S1000)
XuLA - (Spartan 3A XC3S50A, XC3S200A)
XST-4.0 - Extender Board
XSUSB - USB Interfface
Dr Dave Vanden Bout runs a Yahoo mailing list to support his boards http://tech.groups.yahoo.com/group/xsboard-users/
FPGA FAQ
The FPGA Frequently Asked Questions Web site has a more comprehensive list of FPGA Prototye Boards.
3. FPGA Prototyping Boards I Use:
3.1 BurchED B3-Spartan2+ Board
My first FPGA projects used the B3-Spartan2+ board from Burch Electronic Design locate up in Sydney here in Australia. The B3-Spartan2+ used a 200K gate Xilinx XC2S200 and I also used the B3-SRAM 128K x 16bit SRAM module and the B3-FPGA-CPU-IO board for serial communications, keyboard, mouse and VGA video. The B3-Spartan2+ board was replaced by the B5-X300 board which used the larger 300K gate XC2S300E. Neither the B3-Spartan2+ nor the B5-X300 are sold now, although they were sold internationally when they were first introduced.3.1.1 ICST525-01 PLL Clock divider
The B3-Spartan2+ and the B5-X300 boards both use the ICST525 programmable PLL clock chip for the master clock input with 20 MHz reference clock. By configuring jumpers on the pins of the chip you could select a large range of clock frequencies. There is one of these chips on the main B3 and B5-X300 boards, and one on the B3-FPGA-CPU-IO module. The B5-Peripheral-Interconnect module did not have an ICST525 on it.In some of the early projects I used clocks which are multiples of 4.915254 MHz as it is an exact binary multiple of 9600 Baud used by the MiniUart. More recent projects have been designed for a 50MHz system clock as this appears to be commonly used on other FPGA boards which made it earier to port the designs to other FPGA boards. On the designs using a 50 MHz clock, the baud rate clock is derived from a VHDL pre-scaler.
http://www.idt.com/?app=calculators&device=525_01 Frequency calculator web page
The following two pages have been pre-calculated:4.915254 MHz ICST525-01 for Memio and System68 at 9600 Baud
9.830508 MHz ICST525-01 for System68 at 19K2 Baud.
3.1.2 Notes on modifying the B3-SRAM module
On the original B3-SRAM module there was no separate output enable (OE*) and write (WR*) signals for upper and lower byte control. This was because of the limited number of pins on the adjacent 20 pin headers. To perform byte writes, its was matter of reading the full 16 bits and modifying either the upper or lower byte and writing it back. BurchED fixed the problem on the B5-SRAM module. Tony permanently grounded the Output Enable (OE*) pin of the RAM chip and had a single Chip Select (CS*) and separate upper and lower byte write enables (WEU*, WEL*) which essentially become read/write lines.I modified my B3-SRAM module by cutting the WE* track to U1 on the top of the board and the OE* to J2 pin 19 on the bottom of the board. I wired U1 pin 12 to J2 pin 19 which becomes WEL* (J2 pin 18 becomes WEU*) and I grounded the OE* signal on pin 28 of U1 & U2. The pin-outs in the '.ucf' file are for my modified B3-SRAM module and you will have to change them to suit the B5_SRAM. Note The address and chip select lines have been resquenced on the B5_SRAM.
Some of my early designs use the original B3-SRAM module configuration, and some the revised configuration. You will have to check the code to determine which is which.
3.1.3 Notes on adding a CF card.
I added a CF card to the B3-Spartan2+ board by using a CF to IDE adapter from Darkwire Pty Ltd (See section 3.5.1). You can see the CF IDE adapter and cable in the photo above. The CF card was used to run the Flex9 Disk operating system using System09 on the B3 board.I cut up a 40 pin IDE ribbon cable and split the cable so that the 16 data pins (IDE pins 3-18) and ground pin (IDE pin 19) on the 40 pin connector go to the bottom 17 pins of a 20 pin IDC connector for J4. Pin 1 of the 40 pin IDE connector (ide_reset_n) was split off the cable and soldered to pin 4 of the IDC connector of J3.
The control signals (IDE pins 1, 21, 23, 25, 27, 28, 29, 31-40) go to the bottom 16 pins of the 20 pin IDC connector for J3. Note that IDE pins 31-40 directly line up with J3 pins 11-20, however the ground pins between remaining control pins on J3 must be cut off and the remaining wires individually lined up on the connector, which can be a little bit fiddly.
I inserted 4 wires on pins 1-3 of the J3 connector. Pin 1, which is the +3.3V supply rail, was soldered to the power connector of the CF IDE adapter. Pins 2 & 3 of J3 were left disconnected and pin 4 of the J3 connector (ide_reset_n) was soldered to pin 1 of the 40 pin IDE cable as previously stated.
#
# B3 Connector J4
# IDE / CF Interface
# Note that this pin out is NOT consistent with the B5-IDE
# It's called the peripheral bus for consistence with the XESS board
#
#NET '+3.3V' #pin 1 (not used)
#NET 'pb_gclk2' LOC = 'p182'; #pin 2 (not used)
#NET 'pb_spare2' LOC = 'p160'; #pin 3 (not used)
NET 'pb_data<7>' LOC = 'p161'; #pin 4 - ide pin 3
NET 'pb_data<8>' LOC = 'p162'; #pin 5 - ide pin 4
NET 'pb_data<6>' LOC = 'p163'; #pin 6 - ide pin 5
NET 'pb_data<9>' LOC = 'p164'; #pin 7 - ide pin 6
NET 'pb_data<5>' LOC = 'p165'; #pin 8 - ide pin 7
NET 'pb_data<10>' LOC = 'p166'; #pin 9 - ide pin 8
NET 'pb_data<4>' LOC = 'p167'; #pin 10 - ide pin 9
NET 'pb_data<11>' LOC = 'p168'; #pin 11 - ide pin 10
NET 'pb_data<3>' LOC = 'p172'; #pin 12 - ide pin 11
NET 'pb_data<12>' LOC = 'p173'; #pin 13 - ide pin 12
NET 'pb_data<2>' LOC = 'p174'; #pin 14 - ide pin 13
NET 'pb_data<13>' LOC = 'p175'; #pin 15 - ide pin 14
NET 'pb_data<1>' LOC = 'p176'; #pin 16 - ide pin 15
NET 'pb_data<14>' LOC = 'p178'; #pin 17 - ide pin 16
NET 'pb_data<0>' LOC = 'p179'; #pin 18 - ide pin 17
NET 'pb_data<15>' LOC = 'p180'; #pin 19 - ide pin 18
#NET 'ground' #pin 20 - ide pin 19
#
# B3 Connector J3
# IDE / CF Interface
# Note that this pin out is NOT consistent with the B5-IDE
#
#NET '+3.3V' #pin 1 (wired to the power connector)
#NET 'ide_gclk1' LOC = 'p185'; #pin 2 (not used)
#NET 'ide_spare1' LOC = 'p181'; #pin 3 (not used)
NET 'ide_reset_n' LOC = 'p187'; #pin 4 - ide pin 1
NET 'ide_dmarq' LOC = 'p188'; #pin 5 - ide pin 21
NET 'pb_iowr_n' LOC = 'p189'; #pin 6 - ide pin 23
NET 'pb_iord_n' LOC = 'p191'; #pin 7 - ide pin 25
NET 'ide_iordy' LOC = 'p192'; #pin 8 - ide pin 27
NET 'ide_con_csel' LOC = 'p193'; #pin 9 - ide pin 28
NET 'ide_dmack_n' LOC = 'p194'; #pin 10 - ide pin 29
NET 'ide_intrq' LOC = 'p195'; #pin 11 - ide pin 31
NET 'ide_iocs16_n' LOC = 'p199'; #pin 12 - ide pin 32
NET 'pb_addr<1>' LOC = 'p200'; #pin 13 - ide pin 33
NET 'ide_pdiag_n' LOC = 'p201'; #pin 14 - ide pin 34
NET 'pb_addr<0>' LOC = 'p202'; #pin 15 - ide pin 35
NET 'pb_addr<2>' LOC = 'p203'; #pin 16 - ide pin 36
NET 'ide_cs0_n' LOC = 'p204'; #pin 17 - ide pin 37
NET 'ide_cs1_n' LOC = 'p205'; #pin 18 - ide pin 38
NET 'ide_dasp_n' LOC = 'p206'; #pin 19 - ide pin 39
#NET 'ground' #pin 20 - ide pin 40
3.2 BurchED B5-X300-Spartan2e Board
Burch Electronic Design superseded the B3 board with the B5 based around the 300K gate XC2S300E. Like the B3 board the B5-X300 had a number of add on boards such as the B5-SRAM, B5-Peripheral-Interconnect, B5-CF Compact Flash interface, Switch and LED boards. These boards and modules are no longer sold by BurchED and Tony is now focusing on developing FPGA training material. (See section 1).3.3 Digilent Spartan 3 Starter Board
The Spartan 3 starter board, made by Digilent Inc originally used a XC3S200 200K gate device although there is also a XC3S1000 1000K Gate variant available. It has 1MByte of SRAM arranged as 256K x 32 bits. It features VGA connector, RS232 connector, PS/2 Keyboard connector, Push buttons, switches, individual LEDs as well as 4 x 7 segment LED displays. It has 3 x 40 pin expansion connectors for adding on peripheral boards. It also has serial flash for storing your FPGA configuration.
The only real draw back with this board is that there is no program flash memory for mass storage, and there are only 3 bits for the VGA output which means only 8 colours can be displayed unless you add extra DAC resistors.
I have implemented System09 on the 200K gate board and it only just fits. For US$109 it is not a bad buy. The XC3S1000 version of the board from Digilent costs an additional US$50 but gives you much more logic. Gary Becker has used the XC3S1000 version of this board to implement early versions of his Tandy Colour Computer 3 on an FPGA.
3.4 Digilent Spartan 3E Starter Board
The Xilinx Spartan 3E starter board, also made by Digilent Inc uses a XC3S500E FPGA. It has plenty of features, such as Flash Memory, DDR SDRAM, LCD display, ADCs, DACs, RS232, VGA, Ethernet Phy and much more. It has a number of 6 pin headers for adding small 4 bit modules, as well as a Hirose 100 pin FX2 connector, which can be used for add on boards such as the VDEC-1 Video digitizer.
The limitation of the Spartan 3E start board is that there is no SRAM, which means you need a DDR-SDRAM controller core to use it unless you are using EDK. Also, like the Spartan 3 starter board, the VGA connector only has 3 bits for video (one bit for R,G &B) which means there are only 8 colours. There is a modification on Mike J's FPGA Arcade web site that uses some of the pins on the FX2 connector to extend the VGA colour range to 12 bits or 4096 colours by adding additional resistors.
This board was given to me as part of a project to validate my 6809 design. The 6809 design uses the internal Block RAM to implement 32KBytes of RAM and an 8KByte Program ROM. It would be nice to get a DDR RAM controller working for it.
3.5 XESS XSA-3S1000, XST-3.0 & XSUSB
The XSA-3S1000 board from XESS, as the name implies, uses a XC3S1000, 1 million gate Spartan 3 chip. It has a 9 bit (512 colour) VGA output connector as well as a PS/2 keyboard or mouse connector. It has 32MBytes of SDRAM and 4MBits (?) of Flash. The Flash memory is bank selectable and doubles as a FPGA configuration and program code store.
XESS use a CPLD to act as a download controller which connects to the printer port of your computer. You can download FPGA configuration, Flash Program Code, or SDRAM Code using a suite of software utilities. You can also use the Xilinx Parallel IV pod too if you want. XESS also sell a XSUSB module that allows the board to be programmed over USB. XESS have a lot of free example code for the XSA-3S1000 on their web site as well as a SDRAM controller IP for use with the board.
The other good feature of this board is the large number of header pin outs. The board is actually designed to plug into the XST-3.0 carrier board (the XST-4.0 is the current version), but can be used to interface to your own carrier if you desire.
The XSA-3S1000 board was purchased so a group of internet friends could develop a PDP-8 project. The large number of uncommitted I/O pins made the board ideal to interface to switch banks and LED display panels as well as other PDP-8 bus devices.
3.5.1 IDE Compact Flash Interface.
The XST-3.0 board has an IDE interface for adding a hard disk drive. The 16 IDE data pins and IO read/write pins are also used for the ethernet controller and the two expansion slot connectors. I have used a Dual IDE to CF adapter card which I bought from Darkwire here in Australia. Darwire sell a variety of CF, SATA and SD/MMC to IDE adapter cards, although I have only tried the CF card on the XST-3.0.
The IDE interface on the XST-3.0 and XSA-3S1000 does not have 5V protection so it is important that you power the IDE-CF card from 3.3V. I mounted terminals on the 3.3V supply of the XST-3.0 board and powered the CF card off that. The IDE-CF card uses a 3.5' floppy 4 pin power connector which I chopped off an old PC. The red lead is normally the +3.3V and black leads ground, but you should always check for yourself with information on web to ensure that is correct.
3.6 Memec Design / Avnet V4FX12LC & P160 Analog
The Memec Design V4FX12LC board uses the Virtex 4 FX12 FPGA which includes a 200MHz Power PC 405 processor in addition to about 500K gates of programmable logic. This board was purchased for me by work with the idea of doing GPS receiver signal processing. It was bundled with EDK7.1 and BaseX ISE 7.1 as part of the XFest training course offered by Memec in Australia in 2005.
The board features 64MBytes of 16 bit DDR-SDRAM as well as flash memory, push buttons and an LCD display. Monta Vista provide a version of Linux for the ML302 board which should also run on the V4FX12LC board. It is only a demo version, so you have to pay $s if you want to do any Linux development with it. Also Monta Vista Linux on was designed to run with a soft-core Ethernet controller and does not use either of the two Ethernet controllers built into the V4FX12LC. I believe the Ethernet soft-cores on EDK 7.1 are time limited unless you purchase them.
Memec were taken over by Avnet in 2005/6, but last time I saw, Avnet were still offering the P160 add on modules for this board. The Communications 3 module offers SRAM, VGA and PS/2 interfaces, ADCs and DACs as well as communications interfaces. The ADCs and DACs are only useful for audio frequencies however. There is also high speed data acquisition module for a few hundred dollars which work up into the 10s of Msps range.
You can buy a number of commercial cores such as Floating Point Units for the PPC405 for the Virtex 4 but they are too expensive for me. There are FPUs on the open cores web site, but they are not designed to integrate with the APU of the PPC405 to the best of my knowledge. Webpack 8.1 and onwards does include Coregen that includes FPUs, FFTs and so on but I'm not sure how these interface with the PPC405 on the Virtex 4.
It would like to use the V4FX12LC for a software radio:
3.7 Altera / Terasic DE2-70 Cyclone 2 & D5M camera module
Altera / Terasic DE2-70 board running the initial demo design.
Close up of the DE2-70 board with the D5M digital camera on the right.
Tuesday 6th April 2010
I have a new toy, a Terasic DE2-70 board with Altera Cyclone II EP2C70F896 FPGA, 64MB SDRAM x 2, 2MB SSRAM and 8BM Flash, Multimedia interface with dual TV decoders. I plan using two D5M 5Mpixel camera sensors (one shown on the right) to do some stereo vision work. The board is shown running the application shipped with the board.
Cornell University runs the ECE 5760 Advanced Microcontrollers class. They use the Altera/Terasic Cyclone II DE2 board (as opposed to the DE2-70). The following link is to their Final Projects. The head tracking project uses use the D5M camera module. In 2010 the projects included a stereo vision depth mapper.
3.8 Altera / Terasic DE1 Cyclone 2
Altera / Terasic DE1 board running Gary Becker's FPGACoCo3
Tuesday 18th January 2011
I bought a Terasic DE1 board for running Gary Becker's CoCo3FPGA which uses the CPU from my System09 project but adds the GIME and other support logic such as the keyboard and sound interface. The DE1 board has a Cyclone II 20K LE EP2C20 FPGA, 8MBytes of SDRAM, 512KBytes SRAM, 4MBytes of flash, VGA port, RS-232, PS/2 Port, EPCS4 configuration flash, 2 x expansion headers, 24 bit audio CODEC, 27MHz, 50MHz & 24 MHz oscillators, SD Card socket, Altera USB Blaster controller, 8 green LEDs, 10 Red LEDs, 4 x 7 segment displays, 10 toggle switches and 4 push buttons.
3.9 XESS XuLA Spartan 3A
Friday 28th January 2011
Dave vanden Bout sent me a complementary version of his XuLA Spartan 3A 200K gate board. http://xess.com/prods/prod048.php
I have a few old B5 peripheral connector boards that I intend to use to interface to it. The B5 peripheral interconnect boards have an MAX3232 RS232 level converter on it as well as PS/2 keyboard and mouse connectors and a 6 bit VGA resistor DAC (2 bits for each R, G and B signal).
Sunday 5th June 2011
I did get System09 running on the XuLA board. I used wire wrap wire on the B5-Peripheral-Connect board and soldered them to the pins of the XuLA board. I've yet to upload the design files to opencores.org. It only uses half of the SDRAM data bus, and memory is limited to 1MB by the configuration of the DAT.
4. FPGA Design Tools
4.1 Xilinx Web Pack ISE:
The Web Pack ISE design software is available free from Xilinx. The latest versions are around 3GB or so you need a fast internet connection if you want to download it. Alternatively you might want to send off for a DVD from Xilinx. Old versions of the Web Pack ISE software I think are still available on the Xilinx web site.
Altera University Program Flash Memory Demonstration
Most of the project on this web site are hosted on opencores.org due to the limited amount of space on this web site. The Xilinx WebPack ISE software is constantly being updated, so some of the project files on this web site may be out of date. WebPack ISE should update the project file, but if it is too old, then you may need to rebuild it for your version.
4.2 Altera Quartus:
Altera provide Quartus II software for development work with their FPGAs. I have used Quartus II for the System09 implementation on the DE1 board. The first book I bought for learning VHDL was simply called 'VHDL' and was written by Douglas Perry. The book used the Altera software for examples. Altera were the first to make their software free I believe and Xilinx came to the party shortly after.
5. FPGA Projects:
5.1 System16 - My Initial VHDL CPU Project
System16 is only a paper design and is a combination of a 6809 design and a sort of striped down 68000, in terms of the number of registers, addressing mode terminology and bit operators. It was more an exercise in designing a 16 bit CPU for memory that did not have byte access.
5.2 Memio.zip Memory I/O Tool
Memio is a state sequencer for examining and modifying RAM on the B3-Spartan2+ board. It was one of my first projects as you can probably tell from the VHDL code. It was a matter of getting something up and running quickly that allowed me to check the functioning of the B3-SRAM. These days it is so easy to get a microprocessor running with a monitor program that this project is a bit redundant but I have kept the design here as a historic record of my work.
It was developed using Xilinx WebPack ISE 4.2 VHDL tools. It uses a highly hacked version of MiniUart by Ovidiu Lupas which used to be on www.opencores.org
Memio assumes you have the B3-FPGA-CPU-IO card connected to connector J3 and the B3-SRAM card connected to J6 and J9. The current clock divider for the UART assumes a 4.915254 MHz clock for 9600bps serial I/O, which gives a nice round division factor for the clock divider.
Commands for Memio are:
| M <address> | Examine memory location |
| <space bar> <data> | Write 16 bit hexadecimal value |
| N | Display Next memory location |
| P | Display Previous memory location |
For simplicity only the first 64Kwords of SRAM are used (128Kbytes). Address line A16 is grounded. Data words are 16 bits wide. Command keys and hexadecimal values must be all uppercase (although that could easily be changed). All input characters are echoed back out the UART. This is because I could not get Hyperterm to echo characters locally under windows98 SE.
5.3 Micro8 - A very simple microprocessor
Micro8 was based on a minimal set 4 instruction computer by Tim Boscke which was designed to fit in a 32 Macrocell CPLD. Tim's design is now available on the Opencores web site as the MCPU (Minimal CPU) project. http://www.opencores.org/project,mcpu The whole MCPU design fits in a single page.
Tim's computer had only ADD, NOR , STA and JCC instructions and could only address 64 bytes of memory. It had a single carry bit which was set by the JCC (Jump on Carry Clear) instruction. Most basic microprocessor instructions can be built up using these four basic instructions.
For my Micro8 design I have added an 8 bit index register and four addressing modes, Immediate, Absolute, Indexed and PC Relative and I've extended the addressing range from 64 bytes to 2K bytes. The top five bits of the opcode byte determine the operation and addressing mode. The bottom 3 bits of the opcode form the high bits of the address argument. I've also added a Zero (Z) Flag and a Negative (N) flag and conditional branches that do not change the condition codes. Micro8 does not have a return stack and does not support subroutine calls.
Micro8 was implemented on the B3 Spartan2+ board. Although I have included the B3-SRAM in the I/O pin-outs, it does not use the SRAM to print the message. The VHDL code should run quite happily without the B3-SRAM module. I put the I/O interface module on connector J3 of the B3-Spartan2+ board, but its probably better suited to J8.
5.4 Micro8a - Adding a Stack
In my Micro8A I have added a 7 bit stack pointer at $0FF that works down to $080. I've added subroutine calls, Push and Pull registers and interrupts as well as some inherent single byte instructions to operate on the accumulator and index register.5.5 Micro16 - Very Basic 16 bit CPU
Micro16 has 8 instructions and two addressing modes: Direct and Indirect. Direct addressing can address 4K Words of Data or Program space while indirect addressing can address 64K Words of data space. The instruction word is 16 bits wide, with 3 bits used for the instruction, 1 bit used for the addressing mode and 12 bits used to form the Direct address. It has an 8 level hardware stack and one interrupt input. It was intended as a substitute for a compact flash state machine. So far I have not managed to get it to work with the Compact Flash, which is a bit unfortunate given how simple it is. I think the problem may have something to do with the speed at which it accesses Compact Flash.5.6 Micro16 - Processing Array
The idea was to implement an array of Micro16 computing elements with shared block RAM memory.5.7 Motorola 8 bit CPUs
I have coded some of the Motorola 8 bit CPUs, namely the MC6800 and MC6801, MC6805, MC6809 and MC68HC11. These are still works in progress and I have kept a record of their development on their respective web pages.I originally attempted to use the 6809 VHDL design by Flint Weller as a starting point, but it was a bit too complex and too ambitious a project for someone just starting out. For newbies just starting out on VHDL and FPGA design I'd recommend starting with something simpler like the Micro8. You can find Flint's VHDL core on the Flex User Group page under 'File Exchange' however it needs a lot of work.
It was the ambition of one of the Flex User Group members to design a FPGA based Flex system. FLEX is an old disk operating system for the 6800 and 6809. The 6800 and 6809 can only address a maximum of 64KBytes of memory although with the SWTPc 6809 it was extended with what they called a DAT or Dynamic Address Translation, that can map 4K blocks from 1MByte of memory into the 64K addressing space.
Since Flint Weller's 6809 design was too complex to understand, and I think was only intended for simulation, I went back to basics and designed the Micro8, System05 (a 6805 which I still have not completed), System68 (a 6800), System11 (a 68HC11 which is still not finished) and eventually I worked my way up to System09 which is a 6809 System On a Chip. System09 emulates the SWTPc hardware.
The 'System' name was all I could think of at the time and refers to a Systems On a Chip since the design includes peripherals such as ACIA (UART), VDU, PS/2 Keyboard, Dynamic Address Translation, Timers, Parallel I/O etc. as well as the CPU cores. A number of people are using System68 and System09 CPU cores as the basis of pinball and arcade games. See the resources links below for more details.
I have managed to get the Flex 9 Disk operating system running on System09 using a RAM disk and Compact Flash card configured for True IDE mode. Boards with IDE interfaces such as the XESS XSA-3S1000 with XST-3.0 motherboard will operate with a IDE to CF adapter as well. Flex 2 is also available for the 6800, however I have not managed to modify the disk drivers for that yet.
The Flex Users Group has collected most of the old FLEX Software and SWTPc documentation and have archived it. Much of the Flex software was obtained from that archive. If you have any old Flex software, I'm sure the Flex User Group would be interested to hear about it.
5.8 System01 - 6801 - Working (Incomplete I/O)
5.9 System68 - 6800 - Working
5.10 System05 - 6805 - Work in Progress
5.11 System11 - 68HC11 - Partly Working
5.12 System09 - 6809 SOC - Runs Flex9 with VDU and PS/2 keyboard
System09 has been ported to the following Xilinx FPGA development boards:
- BurchED B3-Spartan2+
- BurchED B5-X300
- Digilent Spartan 3 starter board
- Digilent Spartan 3E starter board
- XESS XSA-3S1000 and XST-3.0 carrier board
- XESS XuLA 200 with interface board
System09 has also been ported to the Terasic DE1 board using Altera's Quartus II software.
Recent versions of Xilinx Webpack ISE development software no longer support the Spartan 2 and Spartan 2e devices used on the BurchED B3 and B5 boards.
5.13 System6801 - Wishbone Compliant 6801 for Altera by Michael L. Hasenfratz Sr.
Michael L. Hasenfratz has taken my System01 core and has made it wishbone compliant. He has also added some of the 6801 peripherals at locations $0000 to $001F. The project is being hosted on the OpenCores web site. He has ported it to an Altera FPGA.
Michael has kindly made his Relocatable Macro Assemblers and Linker for the MC6800, MC6809 and MC68HC11 available to the public (as shareware ?). It can be down-loaded here:
RMCAXX.zip
6. VHDL & Verilog IP Resource Links:
http://www.opencores.org Open Cores Repository.
The Open Cores web site is the main web site for open source FPGA cores.
http://www.fpgacpu.org Jan Gray's Risc CPU Web Site
Jan Gray has a XR16 RISC CPU , GR000 RISC CPU and XSOC (System on a Chip). He also runs the FPGA CPU mailing list.
http://www.fpga-faq.com/ Philip Freidin's (Fliptronics) FPGA FAQ.
The FPGA Frequently Asked Questions web site.
http://tech.groups.yahoo.com/group/FPGA_CV/ FPGA Computer Vision
A list I set up to discuss the use of FPGAs for Computer Vision applications
http://instruct1.cit.cornell.edu/courses/ece576/FinalProjects/ Cornell University ECE5760 Advanced Microcontrollers Final Projects
Lots of interesting student projects with demonstration videos.
http://groups.yahoo.com/group/CoCo3FPGA/ Gary Becker's CoCo3 on a FPGA Yahoo Group
Gary Becker is using the CPU from the system09 project for his CoCo3 (Tandy Colour Computer 3) on an FPGA.Gary first ported his CoCo3FPGA project to the XC3S1000 Digilent Spartan 3 starter board but is now mainly using the Terasic DE1 board.
Youtube video of Gary's CoCo3FPGA at the Glenside CoCo Fest 2010 as implemented on an Altera DE1 board
Glenside CoCo Computer Club who host the CoCo Fest.
http://www.edcheung.com/album/album07/Pinball/wpc_sound.htm Edward Cheung's Williams Pinball Controller page
Edward is using CPU09 core with a Digilent Spartan 3A board to implement a Williams Pinball Controller.
http://members.iinet.net.au/~msmcdoug/ Mark's Perpetually WIP Home page
Mark McDougall's Vic20, ZX81, TRS80 and Arcade game web page.
http://pacedev.net/ Programmable Arcade Circuit Emulation.
Forum for FPGA arcade game developers.
http://www.fpgaarcade.com Mike J's FPGA Arcade.
Mike Johnson's complete PACMAN, Space Invaders, and Galaxians in FPGA !
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ John Williams MicroBlaze uCLinux Web Site.
John Williams is a Professor at the School of Information Technology and Electrical Engineering at the University of Queensland. He runs quite an active mailing list for implementing uCLinux on the Xilinx MicroBlaze soft-core processor.
http://www.c-to-verilog.com/ C to Verilog - Automating Circuit Design
C-to-Verilog is a free service for circuit designers.
http://excamera.com/sphinx/fpga-vhdl-verilog.html James Bowman's project page
Verilog examples, home-brew Forth CPU and NTSC composite video generator..
http://excamera.com/sphinx/gameduino/ James Bowman's Gameduino.
Sprite controller for tiny microprocessors such as the Atmel AVR.
http://www.birdcomputer.ca/ Robert Finch's Bird Computer - FPGA Cores
Robert has a variety of CPU, video, audio, timekeeping and keyboard projects for download on his web site.
CPU86 8088 Free FPGA IP Core
HT-LAB FPGA / VHDL / SystemC / Embedded
Various FPGA projects for the hobbyist. Includes information for connecting devices such as LCD Displays and R/C Servos to FPGAs.
http://alexfreed.com/FPGApple/ Interfacing Compact Flash to the Spartan 3 Starter Board
Alex has used a Spartan 3 starter board to implement an Apple II. He has used a Digilent Test Point Header board to connect an IDE CF adapter.
http://www.retromicro.com Doug Hodson's Web Page
Doug has implemented a few projects using the XESS XSA100 FPGA Board. Doug's project page has some examples of VGA video generators. The XSA100 is quite a nice board with Flash memory and Dynamic RAM, although it uses a smaller FPGA and access to static RAM conflicts with some of the I/O pins. The XSA100 uses a XC2S100 FPGA and can be purchased with the XStend prototyping motherboard. For more details check out http://www.xess.com . They have all the manuals on their web site. The XESS documentation is quite good.
http://www.madscientistroom.org/fpga/ Randy Thelen's Mad Scientist Room.
Randy Thelen has a good User Constraint File generator amongst his FPGA bits and pieces.
http://www.6502.org/users/dieter/index.htm Dieter's Homebuilt CPUs.
http://brainwagon.org/ Mark VandeWettering's Homebrew computing and logic blog.
The Dalton Project at the University of California Computer Science Dept in Riversdale have an Intel 8051 core. There is a synopsis model as well as C++ simulator for the 8051.
The Department of Electronic Technology at the University of Valladolid in Spain have an Open DSP design which can be found on their web site.
University of Hamburg VHDL Page. Assorted VHDL tools and microprocessor cores.
Daniel Wallner's PPX16 (PIC16C55, PIC16F84)
Daniel Wallner's T80 (Z80) (actually it's the TV80)
Daniel Wallner's AX8 (90S1200, 90S2313)
Daniel Wallner's T65 (6502)
Daniel Wallner's PPX16 (PIC16C55, PIC16F84)
K Ring Technologies Semiconductor Indi16 16n bit Forth CPU. Designed for Altera Quartus II software.
Green Mountains Computing Systems have a MC68HC11 VHDL core as well as VHDL tools and simulators. I tried compiling this core under the Xilinx ISE 4.1 Webpack software and it used 200% of the XC2S200 resource, so it is not an efficient design. Later versions of Xilinx ISE Webpack may be more efficient.
Chuck McManis has put up a web site with a list of his projects for the B3-SPARTAN2+ board.
For some fun, projects on the net, using Z80 cpus implemented completely in the FPGA. Daniel Wallner's computers using FPGA T80 cores .
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Altera University Program. Flash Memory IP Core. Qsys and Standalone IP Core. 1 Core Overview. A Flash Memory is a non-volatile type of memory that can be electrically erased and reprogrammed. It is similar to volatile types of memory, such as SRAM and DRAM, in that it can be written to and read; however, it is different. Download the free trial version below to get started. Double-click the downloaded file to install the software.
Contents • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Brief history [ ] The AVR architecture was conceived by two students at the (NTH), Alf-Egil Bogen and Vegard Wollan. The original AVR MCU was developed at a local house in, called Nordic VLSI at the time, now, where Bogen and Wollan were working as students.
[ ] It was known as a μRISC (Micro RISC) [ ] and was available as silicon IP/building block from Nordic VLSI. [ ] When the technology was sold to Atmel from Nordic, the internal architecture was further developed by Bogen and Wollan at Atmel Norway, a subsidiary of Atmel.
The designers worked closely with compiler writers at to ensure that the AVR instruction set provided efficient of. Atmel says that the name AVR is not an acronym and does not stand for anything in particular. The creators of the AVR give no definitive answer as to what the term 'AVR' stands for. However, it is commonly accepted that AVR stands for Alf and Vegard's RISC processor. Note that the use of 'AVR' in this article generally refers to the 8-bit RISC line of Atmel AVR Microcontrollers.
Among the first of the AVR line was the AT90S8515, which in a 40-pin DIP package has the same pinout as an microcontroller, including the external multiplexed address and data bus. The polarity of the RESET line was opposite (8051's having an active-high RESET, while the AVR has an active-low RESET), but other than that the pinout was identical. The AVR 8-bit microcontroller architecture was introduced in 1997. By 2003, Atmel had shipped 500 million AVR flash microcontrollers. The platform for simple electronics projects was released in 2005 and featured ATmega8 AVR microcontrollers. Device overview [ ] The AVR is a machine, where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.
Basic families [ ] AVRs are generally classified into following: • tinyAVR – the ATtiny series. Main article: In 2006, Atmel released microcontrollers based on the 32-bit architecture. This is a completely different architecture unrelated to the 8-bit AVR, intended to compete with the -based processors. It has a 32-bit data path, and instructions, along with other audio- and video-processing features.
The instruction set is similar to other RISC cores, but it is not compatible with the original AVR (nor any of the various ARM cores). Device architecture [ ], and are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data memory or memory-mapped devices. Almost all devices (except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips. Program memory [ ] Program instructions are stored in. Although the are 8-bit, each instruction takes one or two 16-bit words.
The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64 KB of flash, while the ATmega32x line has 32 KB). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC AVR/FPGA chips. Internal data memory [ ] The data consists of the, I/O registers, and.
Some small models also map the program ROM into the data address space, but larger models do not. Internal registers [ ].
Atmel ATxmega128A1 in 100-pin package The AVRs have 32 and are classified as 8-bit RISC devices. In the tinyAVR and megaAVR variants of the AVR architecture, the working registers are mapped in as the first 32 memory addresses (0000 16–001F 16), followed by 64 I/O registers (0020 16–005F 16). In devices with many peripherals, these registers are followed by 160 “extended I/O” registers, only accessible as (0060 16–00FF 16). Actual SRAM starts after these register sections, at address 0060 16 or, in devices with 'extended I/O', at 0100 16. Even though there are separate addressing schemes and optimized opcodes for accessing the register file and the first 64 I/O registers, all can also be addressed and manipulated as if they were in SRAM.
The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15 are omitted) which are not addressable as memory locations. I/O memory begins at address 0000 16, followed by SRAM. In addition, these devices have slight deviations from the standard AVR instruction set.
Most notably, the direct load/store instructions (LDS/STS) have been reduced from 2 words (32 bits) to 1 word (16 bits), limiting the total direct addressable memory (the sum of both I/O and SRAM) to 128 bytes. Conversely, the indirect load instruction's (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash and configuration bits; therefore, the LPM instruction is unnecessary and omitted. In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000 16–0FFF 16).
As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (1000 16–1FFF 16). The actual SRAM is located after these ranges, starting at 2000 16. GPIO ports [ ] Each port on a tiny or mega AVR drives up to eight pins and is controlled by three 8-bit registers: DDR x, PORT x and PIN x, where x is the port identifier. • DDR x: Data Direction Register, configures the pins as either inputs or outputs.
• PORT x: Output port register. Sets the output value on pins configured as outputs. Enables or disables the on pins configured as inputs. • PIN x: Input register, used to read an input signal. On some devices, this register can be used for pin toggling: writing a logic one to a PIN x bit toggles the corresponding bit in PORT x, irrespective of the setting of the DDR x bit. XmegaAVR have additional registers for push/pull, totem-pole and pullup configurations.
EEPROM [ ] Almost all AVR microcontrollers have internal for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed. In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions, which makes EEPROM access much slower than other internal RAM. However, some devices in the SecureAVR (AT90SC) family use a special EEPROM mapping to the data or program memory, depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space.
Since the number of writes to EEPROM is limited – Atmel specifies 100,000 write cycles in their datasheets – a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if the contents need to be changed. Note that erase and write can be performed separately in many cases, byte-by-byte, which may also help prolong life when bits only need to be set to all 1s (erase) or selectively cleared to 0s (write).
Program execution [ ] Atmel's AVRs have a two-stage, single-level design. This means the next machine instruction is fetched as the current one is executing.
Most instructions take just one or two clock cycles, making AVRs relatively fast among microcontrollers. The AVR processors were designed with the efficient execution of code in mind and have several built-in pointers for the task. Instruction set [ ].
Main article: The is more than those of most eight-bit microcontrollers, in particular the and with which AVR competes today. However, it is not completely regular: • X, Y, and Z have addressing capabilities that are different from each other. • locations R0 to R15 have more limited addressing capabilities than register locations R16 to R31.
• I/O ports 0 to 31 can be bit addressed, unlike I/O ports 32 to 63. • CLR (clear all bits to zero) affects flags, while SER (set all bits to one) does not, even though they are complementary instructions. (CLR is pseudo-op for EOR R, R; while SER is short for LDI R,$FF.
Math operations such as EOR modify flags, while moves/loads/stores/branches such as LDI do not.) • Accessing read-only data stored in the program memory (flash) requires special LPM instructions; the flash bus is otherwise reserved for instruction memory. Additionally, some chip-specific differences affect code generation.
Code pointers (including return addresses on the stack) are two bytes long on chips with up to 128 KB of flash memory, but three bytes long on larger chips; not all chips have hardware multipliers; chips with over 8 KB of flash have branch and call instructions with longer ranges; and so forth. The mostly regular instruction set makes programming it using C (or even Ada) compilers fairly straightforward. Has included AVR support for quite some time, and that support is widely used. In fact, Atmel solicited input from major developers of compilers for small microcontrollers, to determine the instruction set features that were most useful in a compiler for high-level languages. MCU speed [ ] The AVR line can normally support clock speeds from 0 to 20 MHz, with some devices reaching 32 MHz.
Lower-powered operation usually requires a reduced clock speed. All recent (Tiny, Mega, and Xmega, but not 90S) AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry.
Some AVRs also have a system clock prescaler that can divide down the system clock by up to 1024. This prescaler can be reconfigured by software during run-time, allowing the clock speed to be optimized. Since all operations (excluding multiplication and 16-bit add/subtract) on registers R0–R31 are single-cycle, the AVR can achieve up to 1 per MHz, i.e. An 8 MHz processor can achieve up to 8 MIPS. Loads and stores to/from memory take two cycles, branching takes two cycles.
Branches in the latest '3-byte PC' parts such as ATmega2560 are one cycle slower than on previous devices. Development [ ] AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are sold under various names that share the same basic core, but with different peripheral and memory combinations. Compatibility between chips in each family is fairly good, although I/O controller features may vary. See for sites relating to AVR development. Features [ ] AVRs offer a wide range of features: • Multifunction, bi-directional general-purpose I/O ports with configurable, built-in • Multiple internal oscillators, including RC oscillator without external parts • Internal, self-programmable instruction up to 256 KB (384 KB on XMega) • using serial/parallel low-voltage proprietary interfaces or • Optional boot code section with independent lock bits for protection • On-chip debugging (OCD) support through JTAG or on most devices • The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on. These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP or HVSP.
By default, AVRs with JTAG come with the JTAG interface enabled. • uses the /RESET pin as a bi-directional communication channel to access on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin. • Internal data up to 4 KB • Internal up to 16 KB (32 KB on XMega) • External 64 KB little endian data space on certain models, including the Mega8515 and Mega162. • The external data space is overlaid with the internal data space, such that the full 64 KB address space does not appear on the external bus and accesses to e.g.
Address 0100 16 will access internal RAM, not the external bus. • In certain members of the XMega series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16 MB of data memory to be directly addressed. • 8-bit and 16-bit timers • output (some devices have an enhanced PWM peripheral which includes a dead-time generator) • that record a time stamp triggered by a signal edge • Analog comparator • 10 or 12-bit, with multiplex of up to 16 channels • 12-bit • A variety of serial interfaces, including • compatible Two-Wire Interface (TWI) • Synchronous/asynchronous serial peripherals (/USART) (used with, and more) • (SPI) • Universal Serial Interface (USI): a multi-purpose hardware communication module that can be used to implement an SPI, I 2C or UART interface.
• detection • (WDT) • Multiple power-saving sleep modes • Lighting and motor control (-specific) controller models • controller support • controller support • Proper full-speed (12 Mbit/s) hardware & Hub controller with embedded AVR. • Also freely available low-speed (1.5 Mbit/s) () software emulations • controller support • controller support • Low-voltage devices operating down to 1.8 V (to 0.7 V for parts with built-in DC–DC upconverter) • picoPower devices • controllers and 'event system' peripheral communication. • Fast cryptography support for and Programming interfaces [ ] There are many means to load program code into an AVR chip. The methods to program AVR chips varies from AVR family to family.
Most of the methods described below use the RESET line to enter programming mode. In order to avoid the chip accidentally entering such mode, it is advised to connect a pull-up resistor between the RESET pin and the positive power supply. 6- and 10-pin ISP header diagrams The (ISP) programming method is functionally performed through, plus some twiddling of the Reset line.
As long as the SPI pins of the AVR are not connected to anything disruptive, the AVR chip can stay soldered on a while reprogramming. All that is needed is a 6-pin connector and programming adapter.
This is the most common way to develop with an AVR. The Atmel AVRISP mkII device connects to a computer's USB port and performs in-system programming using Atmel's software.
AVRDUDE (AVR Downloader/UploaDEr) runs on, Windows, and, and supports a variety of in-system programming hardware, including Atmel AVRISP mkII, Atmel JTAG ICE, older Atmel serial-port based programmers, and various third-party and 'do-it-yourself' programmers. PDI [ ] The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of XMEGA devices.
The PDI supports high-speed programming of all non-volatile memory (NVM) spaces; flash, EEPROM, fuses, lock-bits and the User Signature Row. This is done by accessing the XMEGA NVM controller through the PDI interface, and executing NVM controller commands. The PDI is a 2-pin interface using the Reset pin for clock input (PDI_CLK) and a dedicated data pin (PDI_DATA) for input and output. High-voltage serial [ ] High-voltage serial programming (HVSP) is mostly the backup mode on smaller AVRs. An 8-pin AVR package does not leave many unique signal combinations to place the AVR into a programming mode. A 12-volt signal, however, is something the AVR should only see during programming and never during normal operation.
The high voltage mode can also be used in some devices where the reset pin has been disabled by fuses. High-voltage parallel [ ] High-voltage parallel programming (HVPP) is considered the 'final resort' and may be the only way to correct bad fuse settings on an AVR chip. Bootloader [ ] Most AVR models can reserve a region, 256 B to 4 KB, where re-programming code can reside.
At reset, the bootloader runs first and does some user-programmed determination whether to re-program or to jump to the main application. The code can re-program through any interface available, or it could read an encrypted binary through an Ethernet adapter like. Atmel has application notes and code pertaining to many bus interfaces.
ROM [ ] The AT90SC series of AVRs are available with a factory mask-ROM rather than flash for program memory. Because of the large up-front cost and minimum order quantity, a mask-ROM is only cost-effective for high-production runs. AWire [ ] aWire is a new one-wire debug interface available on the new UC3L AVR32 devices. Debugging interfaces [ ] The AVR offers several options for debugging, mostly involving on-chip debugging while the chip is in the target system. DebugWIRE [ ] is Atmel's solution for providing on-chip debug capabilities via a single microcontroller pin. It is particularly useful for lower pin count parts which cannot provide the four 'spare' pins needed for JTAG.
The JTAGICE mkII, mkIII and the AVR Dragon support debugWIRE. DebugWIRE was developed after the original JTAGICE release, and now clones support it. JTAG [ ] The Joint Test Action Group () feature provides access to on-chip debugging functionality while the chip is running in the target system. JTAG allows accessing internal memory and registers, setting breakpoints on code, and single-stepping execution to observe system behaviour. Atmel provides a series of JTAG adapters for the AVR: • The Atmel-ICE is the latest adapter.
It supports JTAG, debugWire, aWire, SPI, TPI, and PDI interfaces. • The JTAGICE 3 is a midrange debugger in the JTAGICE family (JTAGICE mkIII). It supports JTAG, aWire, SPI, and PDI interfaces. • The JTAGICE mkII replaces the JTAGICE and is similarly priced. The JTAGICE mkII interfaces to the PC via USB, and supports both JTAG and the newer debugWIRE interface. Numerous third-party clones of the Atmel JTAGICE mkII device started shipping after Atmel released the communication protocol. • The AVR Dragon is a low-cost (approximately $50) substitute for the JTAGICE mkII for certain target parts.
The AVR Dragon provides in-system serial programming, high-voltage serial programming and parallel programming, as well as JTAG or debugWIRE emulation for parts with 32 KB of program memory or less. ATMEL changed the debugging feature of AVR Dragon with the latest firmware of AVR Studio 4 - AVR Studio 5 and now it supports devices over 32 KB of program memory. • The JTAGICE adapter interfaces to the PC via a standard serial port. [ ] Although the JTAGICE adapter has been declared ' by Atmel, it is still supported in AVR Studio and other tools. JTAG can also be used to perform a test, which tests the electrical connections between AVRs and other boundary scan capable chips in a system. Boundary scan is well-suited for a production line, while the hobbyist is probably better off testing with a multimeter or oscilloscope.
Development tools and evaluation kits [ ]. Atmel STK500 development board Official Atmel AVR development tools and evaluation kits contain a number of starter kits and debugging tools with support for most AVR devices: STK600 starter kit [ ] The STK600 starter kit and development system is an update to the STK500. The STK600 uses a base board, a signal routing board, and a target board.
The base board is similar to the STK500, in that it provides a power supply, clock, in-system programming, an RS-232 port and a CAN (Controller Area Network, an automotive standard) port via DE9 connectors, and stake pins for all of the GPIO signals from the target device. The target boards have sockets for, or packages, depending on the board. The signal routing board sits between the base board and the target board, and routes the signals to the proper pin on the device board. There are many different signal routing boards that could be used with a single target board, depending on what device is in the ZIF socket. The STK600 allows in-system programming from the PC via USB, leaving the RS-232 port available for the target microcontroller. A 4 pin on the STK600 labeled 'RS-232 spare' can connect any TTL level USART port on the chip to an onboard MAX232 chip to translate the signals to RS-232 levels.
The RS-232 signals are connected to the RX, TX, CTS, and RTS pins on the DB-9 connector. STK500 starter kit [ ] The STK500 starter kit and development system features ISP and high voltage programming (HVP) for all AVR devices, either directly or through extension boards.
The board is fitted with DIP sockets for all AVRs available in DIP packages. STK500 Expansion Modules: Several expansion modules are available for the STK500 board: • STK501 – Adds support for microcontrollers in 64-pin TQFP packages. • STK502 – Adds support for LCD AVRs in 64-pin TQFP packages. • STK503 – Adds support for microcontrollers in 100-pin TQFP packages. • STK504 – Adds support for LCD AVRs in 100-pin TQFP packages.
• STK505 – Adds support for 14 and 20-pin AVRs. • STK520 – Adds support for 14 and 20, and 32-pin microcontrollers from the AT90PWM and ATmega family. • STK524 – Adds support for the ATmega32M1/C1 32-pin CAN/LIN/Motor Control family. • STK525 – Adds support for the AT90USB microcontrollers in 64-pin TQFP packages. • STK526 – Adds support for the AT90USB microcontrollers in 32-pin TQFP packages. STK200 starter kit [ ] The STK200 starter kit and development system has a socket that can host an AVR chip in a 40, 20, or 8-pin package.
The board has a 4 MHz clock source, 8 (LED)s, 8 input buttons, an port, a socket for a 32k and numerous general I/O. The chip can be programmed with a dongle connected to the parallel port. Supported microcontrollers (according to the manual) Chip Frequency [MHz] AT90S1200 1k 64 0 12 PDIP-20 AT90S2313 2k 128 128 10 PDIP-20 AT90S/LS2323 2k 128 128 10 PDIP-8 AT90S/LS2343 2k 128 128 10 PDIP-8 AT90S4414 4k 256 256 8 PDIP-40 AT90S/LS4434 4k 256 256 8 PDIP-40 AT90S8515 8k 512 512 8 PDIP-40 AT90S/LS8535 8k 512 512 8 PDIP-40 AVRISP and AVRISP mkII [ ].
AVRISP mkII The AVRISP and AVRISP mkII are inexpensive tools allowing all AVRs to be programmed via. The AVRISP connects to a PC via a serial port and draws power from the target system. The AVRISP allows using either of the 'standard' ICSP pinouts, either the 10-pin or 6-pin connector. The AVRISP has been discontinued, replaced by the AVRISP mkII. The AVRISP mkII connects to a PC via USB and draws power from USB. Visible through the translucent case indicate the state of target power.
As the AVRISP mkII lacks driver/buffer ICs, it can have trouble programming target boards with multiple loads on its SPI lines. In such occurrences, a programmer capable of sourcing greater current is required. Alternatively, the AVRISP mkII can still be used if low-value (~150 ohm) load-limiting resistors can be placed on the SPI lines before each peripheral device. AVR Dragon [ ]. AVR Dragon with and attached, blue/greenish The Atmel Dragon is an inexpensive tool which connects to a PC via USB. The Dragon can program all AVRs via JTAG, HVP, PDI, or ICSP. The Dragon also allows debugging of all AVRs via JTAG, PDI, or debugWire; a previous limitation to devices with 32 KB or less program memory has been removed in AVR Studio 4.18.
The Dragon has a small prototype area which can accommodate an 8, 28, or 40-pin AVR, including connections to power and programming pins. There is no area for any additional circuitry, although this can be provided by a third-party product called the 'Dragon Rider'. JTAGICE mkI [ ] The In Circuit Emulator (JTAGICE) debugging tool supports on-chip debugging (OCD) of AVRs with a JTAG interface. The original JTAGICE mkI uses an RS-232 interface to a PC and can only program AVR's with a JTAG interface. The JTAGICE mkI is no longer in production, however it has been replaced by the JTAGICE mkII.
JTAGICE mkII [ ] The JTAGICE mkII debugging tool supports on-chip debugging (OCD) of AVRs with SPI, JTAG, PDI, and debugWIRE interfaces. The debugWire interface enables debugging using only one pin (the Reset pin), allowing debugging of applications running on low pin-count microcontrollers.
The JTAGICE mkII connects using USB, but there is an alternate connection via a serial port, which requires using a separate power supply. In addition to JTAG, the mkII supports ISP programming (using 6-pin or 10-pin adapters). Both the USB and serial links use a variant of the STK500 protocol. JTAGICE3 [ ] The JTAGICE3 updates the mkII with more advanced debugging capabilities and faster programming. It connects via USB and supports the JTAG, aWire, SPI, and PDI interfaces. The kit includes several adapters for use with most interface pinouts. [ ] The AVR ONE!
Is a professional development tool for all Atmel 8-bit and 32-bit AVR devices with On-Chip Debug capability. Download Highschool Dxd Ova Episode 3 Sub Indo more. It supports SPI, JTAG, PDI, and aWire programming modes and debugging using debugWIRE, JTAG, PDI, and aWire interfaces. Butterfly demonstration board [ ].
Main article: The very popular AVR Butterfly demonstration board is a self-contained, battery-powered computer running the Atmel AVR ATmega169V microcontroller. It was built to show-off the AVR family, especially a then new built-in LCD interface. The board includes the LCD screen, joystick, speaker, serial port, real time clock (RTC), flash memory chip, and both temperature and voltage sensors. Earlier versions of the AVR Butterfly also contained a CdS; it is not present on Butterfly boards produced after June 2006 to allow compliance. The small board has a shirt pin on its back so it can be worn as a name badge.
The AVR Butterfly comes preloaded with software to demonstrate the capabilities of the microcontroller. Factory firmware can scroll your name, display the sensor readings, and show the time. The AVR Butterfly also has a piezoelectric transducer that can be used to reproduce sounds and music. The AVR Butterfly demonstrates LCD driving by running a 14-segment, six alpha-numeric character display. However, the LCD interface consumes many of the I/O pins. The Butterfly's ATmega169 CPU is capable of speeds up to 8 MHz, but it is factory set by software to 2 MHz to preserve the button battery life.
A pre-installed bootloader program allows the board to be re-programmed via a standard RS-232 serial plug with new programs that users can write with the free Atmel IDE tools. AT90USBKey [ ] This small board, about half the size of a business card, is priced at slightly more than an AVR Butterfly. It includes an AT90USB1287 with (OTG) support, 16 MB of, LEDs, a small joystick, and a temperature sensor. The board includes software, which lets it act as a (its documentation is shipped on the DataFlash), a USB joystick, and more.
To support the USB host capability, it must be operated from a battery, but when running as a USB peripheral, it only needs the power provided over USB. Only the JTAG port uses conventional 2.54 mm pinout. All the other AVR I/O ports require more compact 1.27 mm headers. The AVR Dragon can both program and debug since the 32 KB limitation was removed in AVR Studio 4.18, and the JTAGICE mkII is capable of both programming and debugging the processor. The processor can also be programmed through USB from a Windows or Linux host, using the USB 'Device Firmware Update' protocols.
Atmel ships proprietary (source code included but distribution restricted) example programs and a USB protocol stack with the device. Is a third-party () USB protocol stack for the USBKey and other 8-bit USB AVRs. Raven wireless kit [ ] The RAVEN kit supports wireless development using Atmel's chipsets, for and other wireless stacks. It resembles a pair of wireless more-powerful Butterfly cards, plus a wireless USBKey; and costing about that much (under $US100). All these boards support JTAG-based development.
The kit includes two AVR Raven boards, each with a 2.4 GHz transceiver supporting IEEE 802.15.4 (and a freely licensed ZigBee stack). The radios are driven with ATmega1284p processors, which are supported by a custom segmented LCD display driven by an ATmega3290p processor. Raven peripherals resemble the Butterfly: piezo speaker, DataFlash (bigger), external EEPROM, sensors, 32 kHz crystal for, and so on. These are intended for use in developing remote sensor nodes, to control relays, or whatever is needed.
The USB stick uses an AT90USB1287 for connections to a USB host and to the 2.4 GHz wireless links. These are intended to monitor and control the remote nodes, relying on host power rather than local batteries. Third-party programmers [ ] A wide variety of third-party programming and debugging tools are available for the AVR.
These devices use various interfaces, including RS-232, PC parallel port, and USB. Atmel AVR usage [ ]. • Since 1996, NTH has become part of the (NTNU) • blog • ^. • ^ Myklebust, Gaute. Atmel Norway.. Retrieved 2012-09-19. Archived from on 2012-06-23.
Retrieved 2012-09-19. • Atmel press release.. • 2012-11-27 at the.
• • • (PDF).. Retrieved 10 June 2014.
Retrieved 10 June 2014. Retrieved 10 June 2014. Retrieved 10 June 2014. • (PDF) (application note). Atmel Corporation.
Retrieved 14 Jun 2015. The reset line has an internal pull-up resistor, but if the environment is noisy it can be insufficient and reset can therefore occur sporadically. Retrieved 2012-09-19. Retrieved 2012-09-19.
Archived from on 2009-10-12. Retrieved 2012-09-19. Retrieved 2012-09-19. Retrieved 2012-09-19. Retrieved 2012-09-19. Retrieved 2012-09-19. Retrieved 2012-09-19.
Retrieved 2012-09-19. Retrieved 2015-09-11. Retrieved 2012-09-19. Archived from on 15 February 2013.
Retrieved 13 January 2013. Retrieved 2012-09-19. Retrieved 13 January 2013. • 2011-07-07 at the. Archived from on 15 February 2013.
Retrieved 13 January 2013. Retrieved 7 November 2011. Retrieved 2012-09-19. Retrieved 2012-09-19.
Four Walled Cubicle. Retrieved 2012-09-19. • See for a comprehensive list. Comfile Technology, Inc.
Retrieved 13 January 2013. Retrieved 13 January 2013. NetMedia, Inc. Retrieved 13 January 2013. Retrieved 13 January 2013. Retrieved 13 January 2013. Solutions GmbH.
Retrieved 13 January 2013. Schneider Electric Motion USA.
Retrieved 2012-09-19. Retrieved 2012-09-19.
Retrieved 2012-09-19. Retrieved 2015-02-16. LogicGreen Technologies, a clone of the ATmega88.
• [Microcontrollers] (in Russian). Voronezh: OAO 'NIIET'. Swf To Screensaver Scout Keygen Idm here.
Retrieved 22 August 2017. Further reading [ ] • AVR Microcontroller and Embedded Systems: Using Assembly and C; Muhammad Ali Mazidi, Sarmad Naimi, Sepehr Naimi; 792 pages; 2010;. • Embedded C Programming and the Atmel AVR; Richard H Barnett, Sarah Cox, Larry O'Cull; 560 pages; 2006;. • C Programming for Microcontrollers Featuring ATMEL's AVR Butterfly and WinAVR Compiler; Joe Pardue; 300 pages; 2005;.
Altera University Program Flash Memory Demons
• Atmel AVR Microcontroller Primer: Programming and Interfacing; Steven F Barrett, Daniel Pack, Mitchell Thornton; 194 pages; 2007;. • Arduino: A Quick Start Guide; Maik Schmidt; 276 pages; 2011;.
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